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COMPUTER SCIENCE & TECHNOLOGY • COMPUTING

Direct-Mapped Cache

Step through a memory trace and watch each word address split into block offset, cache index and tag while cache lines fill, hit and conflict.

● MEMORY TRACEDirect-Mapped Cache
Hit rate
Hits
Compulsory misses
Conflict misses

Reasoning inspector

live internal state
Cache lines—
Block size—
Current address—
Memory block—
Cache index—
Tag—
Block offset—
Access result—

Follow the address bits

A direct-mapped cache has only one possible line for each memory block. Step through the trace to see why matching an index is not enough—the stored tag must match too.

LEARN WITH THE SIMULATION

Understand Direct-Mapped Cache by experimenting.

START HERE

A direct-mapped cache translates each memory address into three different pieces of information: a block offset, a cache-line index and a tag. This laboratory makes those hidden address fields visible while a reproducible memory trace runs. Each access updates the selected line, classifies the result as a hit, compulsory miss or conflict miss, and exposes why two frequently reused blocks can still evict each other even when much of the cache is empty.

BUILD THE IDEA

What you should understand first

  • Decompose a word address into block, cache index, tag and block offset.
  • Explain why an index chooses where to look while the tag decides whether the desired block is actually present.
  • Distinguish compulsory misses from repeated-block conflict misses in a direct-mapped cache.
  • Relate block size and line count to locality, bit allocation and the collision pattern of a memory trace.

TRY IT YOURSELF

How can a program repeatedly access the same data and still miss in a cache with unused lines?

  1. Use the default trace and step until the first repeated address becomes a hit.
  2. Change the trace so two blocks map to the same index but carry different tags, then alternate them.
  3. Watch the selected cache line flip between tags while other lines remain unused.
  4. Increase the line count or change the block size and see whether the conflict pattern disappears.
Read the visual:

Direct mapping gives each block exactly one legal destination. Reuse helps only if another block mapping to that same line has not replaced it. More total cache capacity does not automatically help unless it changes the mapping relationship relevant to the conflicting blocks.

WHY IT WORKS 01

Index answers where; tag answers which

A direct-mapped cache never searches every line. The index bits select one line immediately. That makes lookup simple and fast, but it creates ambiguity because many memory blocks share the same index. The tag stored with the line resolves that ambiguity. If the selected line is valid and its tag matches the address tag, the access hits; otherwise the requested block must replace what is there.

WHY IT WORKS 02

Why conflict misses exist

Two blocks whose block numbers differ by a multiple of the number of cache lines map to the same direct-mapped index. If a trace alternates between them, each reference can evict the block needed by the next reference. This behavior is a mapping conflict rather than a shortage of total unused lines. The inspector exposes block, index and tag so the collision can be predicted before stepping.

WHY IT WORKS 03

Block size changes more than capacity per line

Increasing the number of words per block moves more low-order address bits into the offset field. Nearby word addresses can then belong to the same block and benefit from spatial locality, but fewer distinct blocks fit in a fixed-size cache and the set of possible index patterns changes. The tradeoff is therefore about both locality and mapping pressure, not merely about loading more data at once.

DO NOT MIX THESE UP

Common misconception

A matching cache index is not a cache hit. The line's valid bit and tag must also match the requested block. A repeated address is not guaranteed to hit, because another block can replace it between accesses. Block size can improve spatial locality, but larger blocks also consume more of the cache and change which address bits belong to the offset and index.

PRACTICE CHALLENGE

Can you design two traces with the same addresses but very different hit rates?

  • Create a short trace with strong temporal reuse that does not create repeated index conflicts.
  • Record the hit rate after the full trace.
  • Reorder the same or similar block references so two blocks repeatedly contend for one line.
  • Use the block/index/tag inspector to explain every new conflict miss rather than judging only the final percentage.
Reveal the reasoning

Hit rate depends on access order as well as the set of addresses. Temporal reuse produces hits only when the reused block survives until its next access. Alternating blocks that map to the same direct-mapped index destroys that reuse and turns later accesses into conflict misses.

MODEL BOUNDARIES

What this simulation assumes

Every simulation simplifies reality or a mathematical system. These are the assumptions and limits to keep in mind while interpreting the results.

Model assumptions

  • Memory addresses are nonnegative 16-bit word addresses and blocks contain a power-of-two number of words.
  • The cache is direct mapped, starts empty and uses a power-of-two number of cache lines.
  • Every miss immediately installs the referenced block in its unique mapped cache line before the next access.

Model limitations

  • Associative caches, replacement policies, write policies, prefetching, multilevel caches and coherence are not represented.
  • The model classifies repeated-block misses as conflicts and does not model capacity misses independently from a fully associative reference cache.

CONNECT IT

Where this matters

  • CPU cache and memory-hierarchy design
  • Reasoning about locality in loops and array traversals
  • Performance debugging for cache-sensitive code
  • Embedded systems and low-level computer architecture

WORDS THAT MATTER

Key vocabulary

Cache line
One direct-mapped cache location that can hold a memory block together with a valid bit and tag.
Block offset
Low-order address information selecting a word within the current memory block.
Index
Address field that selects the one cache line a direct-mapped block is allowed to occupy.
Tag
High-order address information stored with a cache line to identify which mapped memory block is currently present.
Compulsory miss
Miss on the first reference to a block in the modeled trace.
Conflict miss
Miss caused when a previously seen block was displaced by another block mapping to the same direct-mapped line.